1. Field of the Invention
The present invention relates to an ECL (or CML) circuit and more particularly to an ECL circuit permitted to operate at a low voltage.
2. Description of the Background Art
FIG. 5 is a block diagram of a conventional frequency divider. The frequency divider 1 comprises a multiplicity of connected flip-flop circuits 2. A first flip-flop circuit 2 receives a clock signal CLK and also receives a ground potential through a coupling capacitance 3. Outputs Q and Q of the first flip-flop circuit 2 arc inputted to inputs T and T of a second flip-flop circuit 2. In this fashion, outputs of a flip-flop circuit are sequentially propagated to inputs of the next flip-flop circuit until outputs Q and Q of the last flip-flop circuit 2 output a clock signal and an inverted clock signal which arc obtained by frequency-dividing the clock signal CLK.
FIG. 6 is a circuit diagram of a flip-flop circuit of ECL structure in the form of an integrated circuit on a semiconductor chip. The flip-flop circuit 2 of FIG. 6 comprises an ECL circuit portion 11, and a buffer circuit portion 300.
The ECL circuit portion 100 comprises a differential pair of NPN transistors 11 and 12 in a master portion and a differential pair of NPN transistors 13 and 14 in a slave portion. The base of the transistor 11 is connected to a T input terminal, and the base of the transistor 12 is connected to a T input terminal. The base of the transistor 13 is connected to the T input terminal, and the base of the transistor 14 is connected to the T input terminal. The emitters of the transistors 11 and 12 arc connected in common, and the common connection is grounded through a constant-current source NPN transistor 15 for supplying an operating bias current of the master potion and through a resistor 17. The emitters of the transistors 13 and 14 are connected in common, and the common connection is grounded through a constant-current source NPN transistor 16 for supplying an operating bias current of the slave portion and through a resistor 18. The bases of the transistors 15 and 16 are connected in common to a V.sub.CB terminal. A common base potential V.sub.CB generated in a bias circuit (not shown) is applied as a control potential to the V.sub.CB terminal.
In the master potion, a differential pair of NPN transistors 19 and 20 are connected to the collector of the transistor 11, and a differential pair of NPN transistors 21 and 22 are connected to the collector of the transistor 12. In the slave portion, a differential pair of NPN transistors 23 and 24 are connected to the collector of the transistor 13, and a differential pair of NPN transistors 25 and 26 are connected to the collector of the transistor 14.
The emitters of the transistors 19 and 20 are connected in common to the collector of the transistor 11. The base of the transistor 19 is connected to the collector of the transistor 20, and the base of the transistor 20 is connected to the collector of the transistor 19. The emitters of the transistors 21 and 22 are connected in common to the collector of the transistor 12. The collector of the transistor 21 is connected to the collector of the transistor 19 and is connected to a power supply potential V.sub.CC through a node N1 and a resistor 27. The base of the transistor 271 is connected to the power supply potential V.sub.CC through a node N4 and a resistor 30. The collector of the transistor 22 is connected to the collector of the transistor 20 and is connected to the power supply potential V.sub.CC through a node N2 and a resistor 28. The base of the transistor 22 is connected to the power supply potential V.sub.CC through anode N3 and a resistor 29.
The emitters of the transistors 25 and 26 are connected in common to the collector of the transistor 14. The base of the transistor 25 is connected to the collector of the transistor 26, and the base of the transistor 26 is connected to the collector of the transistor 25. The emitters of the transistors 23 and 24 are connected in common to the collector of the transistor 13. The collector of the transistor 23 is connected to the collector of the transistor 25 and is connected to the power supply potential V.sub.CC through the node N3 and the resistor 29. The base of the transistor 23 is connected to the power supply potential V.sub.CC through the node N1 and the resistor 27. The collector of the transistor 24 is connected to the collector of the transistor 26 and is connected to the power supply potential V.sub.CC through the node N4 and the resistor 30. The base of the transistor 24 is connected to the power supply potential V.sub.CC through the node N2 and the resistor 28.
The buffer circuit portion 300 comprises emitter follower NPN transistors 38 and 39. The base of the transistor 38 is connected to the node N3, and the collector thereof is connected to the power supply potential V.sub.CC. The base of the transistor 39 is connected to the node N4, and the collector thereof is connected to the power supply potential V.sub.CC. The emitter of the transistor 38 is connected to a Q output terminal and is grounded through a constant-current source NPN transistor 40 and a resistor 42. The emitter of the transistor 39 is connected to a Q output terminal and is grounded through a constant-current source NPN transistor 41 and a resistor 43. The bases of the transistors 40 and 41 are connected to the V.sub.CB terminal in common with the bases of the transistors 15 and 16.
The operation of the flip-flop circuit 2 of FIG. 6 is classified into four modes to be described below.
In a first mode, input/output levels are as follows: T="L", T="H", Q="L", and Q="H". At that time, the transistors 11, 13, 19 and 24 turn on. This provides a current path of resistor 27--transistor 19--transistor 11--transistor 15--resistor 17, and a current path of resistor 30--transistor 24--transistor 13--transistor 16--resistor 18. The levels at the nodes N1, N2, N3 and N4 are "L", "H", "H" and "L", respectively.
In a second mode, input/output levels are as follows: T="H", T="L", Q="L", and Q="H". At that time, the transistors 12, 14, 22 and 26 turn on. This provides a current path of resistor 28--transistor 22--transistor 12--transistor 15--resistor 17, and a current path of resistor 30--transistor 26--transistor 14--transistor 16--resistor 18. The levels at the nodes N1, N2, N3 and N4 are "H", "L", "H" and "L", respectively.
In a third mode, input/output levels are as follows: T="L", T="H", Q="H", and Q="L". At that time, the transistors 11, 13, 20 and 23 turn on. This provides a current path of resistor 28--transistor 20--transistor 11--transistor 15--resistor 17, and a current path of resistor 29--transistor 23--transistor 13--transistor 16--resistor 18. The levels at the nodes N1, N2, N3 and N4 are "H", "L", "L" and "H", respectively.
In a fourth mode, input/output levels are as follows: T="H", T="L", Q="H", and Q="L". At that time, the transistors 12, 14, 21 and 25 turn on. This provides a current path of resistor 27--transistor 21--transistor 12--transistor 15--resistor 17, and a current path of resistor 29--transistor 25--transistor 14--transistor 16--resistor 18. The levels at the nodes N1, N2, N3 and N4 are "L", "H", "L" and "H", respectively.
By repeating the first to fourth modes in order, the signals inputted to the T and T input terminals are frequency-divided to half, and the resultant signals are outputted from the Q and Q output terminals. The signals at the Q and Q output terminals are inputted to the T and T input terminals of the succeeding flip-flop circuit 2. A need exists at that time for provision of the Q and Q output signals at a potential level which does not allow the respective transistors of the succeeding flip-flop circuit 2 to enter 8 saturation region, which will be described below.
In the second mode, for example, the signals at the "H" and "L" levels are inputted to the T and T input terminals, respectively. The "H" level applied to the T input terminal is derived from the Q output terminal of the preceding flip-flop circuit 2. A potential V.sub.Q(H) at the "H" level is expressed as: EQU V.sub.Q(H) =V.sub.CC -V.sub.BE ( 1)
where V.sub.BE is a base-emitter voltage of a transistor.
At this time, an emitter potential V.sub.E12 of the transistor 12 is: EQU V.sub.E12 =V.sub.Q(H) -V.sub.BE =V.sub.CC -2V.sub.BE ( 2)
Taking into consideration the base-emitter voltage V.sub.BE of the transistor 22 that is on, a collector potential V.sub.C12 of the transistor 12 is: EQU V.sub.C12 =V.sub.CC -V.sub.BE ( 3)
From Expressions (2) and (3), a collector-emitter voltage V.sub.CE12 of the transistor 12 is given as: EQU V.sub.CE12 =V.sub.C12 -V.sub.E12 =V.sub.BE ( 4)
FIG. 7 illustrates an operating characteristic of general transistors, the abscissa being the collector-emitter voltage V.sub.CE, the ordinate being a collector current I.sub.c. To operate a transistor in an active region, not in the saturation region, it is necessary that the collector-emitter voltage V.sub.CE is not less than a saturation voltage V.sub.SAT.
For non-saturation of the transistor 12, it is necessary to satisfy the following condition: EQU V.sub.CE12 &gt;V.sub.SAT ( 5)
From Expression (4) is derived: EQU V.sub.BE &gt;V.sub.SAT ( 6)
This is the first requirement.
On the other hand, a collector potential V.sub.C15 of the transistor 15 is: EQU V.sub.C15 =V.sub.E12 =V.sub.CC -2V.sub.BE ( 7)
The emitter potential V.sub.E15 of the transistor 15 is: EQU V.sub.E15 =V.sub.CB -V.sub.BE ( 8)
Thus a collector-emitter voltage V.sub.CE15 of the transistor 15 is given as: EQU V.sub.CE15 =V.sub.C15 -V.sub.E15 =V.sub.CC -V.sub.CB -V.sub.BE ( 9)
For non-saturation of the transistor 15, it is necessary to satisfy the following condition: EQU V.sub.CE15 &gt;V.sub.SAT ( 10)
From Expression (9) is derived: EQU V.sub.CC &gt;V.sub.CB +V.sub.BE +V.sub.SAT ( 11)
This is the second requirement.
Generally V.sub.BE =0.75 V and V.sub.SAT =0.3 V. The potential V.sub.CB requires at least the amount of on-voltage of the constant-current source transistor 15, so that it is necessary that V.sub.CB =1 V when the temperature characteristics of the on-voltage are taken into consideration. Substituting these values in Expression (11) indicative of the second requirement, then: EQU V.sub.CC &gt;1+0.75+0.3=2.05(V) (12)
That is, the power supply voltage V.sub.CC of the flip-flop circuits 2 must be more than 2.05 V in order that the respective transistors are not saturated but operate in the active region.
The first requirement indicated by Expression (6) is constantly satisfied independently of the power supply voltage V.sub.CC.
Although the above description is associated with the transistor 12, the same is true for the other transistors 11, 13 and 14.
If the power supply voltage V.sub.CC is less than 2.05 V, the transistors 11, 12, 13, 14 are saturated to cause switching delay, resulting in abnormal operation of the flip-flop circuits 2.
The frequency divider 1 of FIG. 5 is in sonic cases used for a device 4 driven by a battery such as a portable telephone as tier example shown in FIG. 8. The power supply voltage V.sub.CC of the frequency divider 1 is, as above described, limited to V.sub.CC &gt;2.05 V. An external battery 5 of the device 4 might have a relatively low voltage. In such a case it is necessary to provide a booster circuit 6 in the device 4 to satisfy the condition of V.sub.CC &gt;2.05 V. This presents a problem of complexity of device structure.